VHDL code For Full Subtractor and Half Subtractor

Full Subtractor and Half Subtractor

FULL SUBTRACTOR 

Full subtractor is a  combinational circuit that perform subtraction of three input bits namely minuend bit A, subtrahend bit B, and borrow in C. The full subtractor generates two output bits: the difference D and borrow out B_OUT.

LOGIC DIAGRAM FOR FULL SUBTRACTOR

LOGIC DIAGRAM FOR FULL SUBTRACTOR

TRUTH TABLE FOR FULL SUBTRACTOR

Truth table

VHDL code for Full Subtractor:

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

1. entity full subtractor is
2.  Port ( A : in STD_LOGIC;
3.  B : in STD_LOGIC;
4.  C : in STD_LOGIC;
5.  diff : out STD_LOGIC;
6.  borrow : out STD_LOGIC);
7. end full subtractor ; 
8. architecture behavioral of full subtractor _is 
9. begin 
10.  diff <= A XOR B XOR C ;
11.  borrow <= (A AND B) OR (B AND (not C) OR (A AND (not C)); 
12.  end behavioral;

Half subtractor :

The half subtractor is a combinational circuit that is used to subtracts two bits. It has two inputs, the minuend A and subtrahend B and two outputs the difference D and borrow out B_OUT. The borrow out  is set when the subtractor needs to borrow from the next digit in a multi-digit subtraction. That is, B_OUT  = 1 when A < B. We know that, A and B are bits, B_OUT  = 1 When A= 0 and B=1.

LOGIC DIAGRAM FOR HALF SUBTRACTOR

LOGIC DIAGRAM FOR HALF SUBTRACTOR

TRUTH TABLE FOR HALF SUBTRACTOR

TRUTH TABLE 

VHDL code for Half Subtractor:

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

1.  entity Half subtractor is
2.  Port ( A : in STD_LOGIC;
3.  B : in STD_LOGIC;
4.  diff : out STD_LOGIC;
5.  borrow : out STD_LOGIC);
6.  end Half subtractor ;
7.  architecture behavioral of Half subtractor _is
8.   begin
9.  diff <= A XOR B ;
10.  borrow <= A AND(not B);
11.  end behavioral;