VHDL Code for 2 to 4 Decoder and 4 to 2 Encoder

VHDL Code for 2 to 4 Decoder and 4 to 2 Encoder :

1) Decoder 
 A Decoder is a logic circuit that is used to converts binary information form n input line to 2ⁿ unique output lines.

• Binary Decoder has n-bit input lines and 2 Power n (2ⁿ) output lines.
• The decoder can be represented in the form of  2 to 4 , 3 to 8 and 4 to 16 line configuration.
• Binary decoder is  constructed by using logic gates.

Two to four Decoder:

 In 2 to 4 decoder, the two inputs are decoded into four outputs,each representing one of the minterms of the two input variable.

Block Diagram for 2 to 4 Decoder

BLOCK DIAGRAM

Logic Diagram for 2 to 4 Decoder 

Truth Table for 2 to 4 Decoder  

TRUTH TABLE

VHDL Code for 2 to 4 Decoder  

Using if else statement

Library IEEE ;

use IEEE.STD_LOGIC_1164

entity decoder is

port(a : in STD_LOGIC_VECTOR(1 downto 0);

       b : out STD_LOGIC_VECTOR(3 downto 0) );

 end decoder ;

Architecture behavioral of  decoder is

begin

Process(a)

begin

if (a = “00”)then

b <=”0001” ;

elsif (a= “01”)then

b <=”0010” ;

elsif (a= “10”)then

b <=”0100” ;

else

b <=”1000” ;

end if ;

end process ;

end behavioral ;


2) Encoder

• An encoder is a combinational circuit that converts information into coded form.
• It has 2ⁿ  (or fewer) input lines and n output lines.

Block Diagram for 4 to 2 Encoder

BLOCK DIAGRAM FOR 4 to 2 ENCODER 

Logic Diagram for 4 to 2 Encoder

CIRCUIT DIAGRAM

Truth Table for 4 to 2 Encoder

TRUTH TABLE

VHDL Code for 4 to 2 Encoder  

library IEEE ;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL ;

use IEEE.STD_LOGIC_UNSIGNED.ALL ;

entity encoder is

port (a: in STD_LOGIC_VECTOR(3 downto 0) ;

         b : out STD_LOGIC_VECTOR(1 downto 0) ) ;

end encoder ;

Architecture behavioral of encoder is

begin

process(a)

begin

if (a(0) = ‘1’) then

b <= ”00” ;

elsif (a(1) = ‘1’) then

b <= ”01” ;

elsif (a(2) = ‘1’) then

b <= ”10” ;

elsif (a(3) = ‘1’) then

b <= ”11” ;

end if ;

end process ;

end behavioral ;