VHDL Code for Full Adder and Half Adder

Full Adder
Full adder is a combinational logic circuit, it is used to add three input binary bits. It contains three inputs and  two outputs sum and carry.

The boolean expressions for these output are: 
Sum  = A⊕B⊕C
Carry = AB + AC + BC

CIRCUIT DIAGRAM FOR FULL ADDER

Truth Table

The Truth-Table Summarizes the circuit operation. Here A, B and Cin are the three bits being added. 
In case of full Adder, the Sum is 1 only when the number of input 1 is odd.
The carry is 1 when two or more input is 1.

VHDL CODE FOR FULL ADDER :

   1. library IEEE;

 2. use IEEE.STD_LOGIC_1164.ALL;

 3. entity full_adder is

 4. Port ( A : in STD_LOGIC;

 5. B : in STD_LOGIC;

 6. Cin : in STD_LOGIC;

 7. S : out STD_LOGIC;

 8. Cout : out STD_LOGIC);

 9. end full_adder ;

 10. architecture behavioral of full_adder_is

 11. begin

 12. S <= A XOR B XOR Cin ;

 13. Cout <= (A AND B) OR (Cin AND A) OR (Cin AND B) ;

 14. end behavioral;

HALF ADDER 
 Half Adder is used to  add  two single binary digits A and B. It has two outputs lines , sum (S) and carry (C). The carry signal represents an overflow into the next digit of a multi-digit addition.

The boolean expressions for these outputs are :
Sum = A⊕ B
Carry = AB

CIRCUIT DIAGRAM FOR HALF ADDER

TRUTH TABLE FOR HALF ADDER

In Truth Table, you can see that the Sum is 1 only when A and B are different.

The Carry output is 1 when A and B are 1.

The Truth-Table summarizes the operation.When A and B are 0, the sum is 0 with carry is 0.

VHDL Code For Half Adder:

1. library ieee;
2. use ieee.std_logic_1164.all;
3. 
   
4. entity HALF_ADDER is 
5. port ( A, B : in bit;
6. SUM, CARRY : out bit);
7. end HALF_ADDER;
8. 
   
9. architecture dataflow of HALF_ADDER is
10. 
    
11. begin
12. SUM < = A xor B;
13. CARRY < = A and B;
14. 
    
15. end dataflow;