VHDL Code For 8 to 1 Multiplexer and 1 to 8 Demultiplexer

VHDL Code For 8:1 Multiplexer

VHDL Code For Mux(MULTIPLEXER) and  Demux(DEMULTIPLEXER)

Multiplexer

• Multiplexer is a combinational circuit that selects binary information from one of many inputs lines and directs it to a single output line.
• The selection of a particular input line is controlled by a group of selection lines.
• There are 2ⁿ input lines and n selection lines whose bit combination determine which input is to be selected.

8 x 1 Multiplexer 
In 8 x 1 Multiplexer, 8 represents number of inputs and 1 represents output line. So three (3) select lines are required to select one of the inputs.

Logic Diagram of 8 to 1 Multiplexer 

LOGIC DIAGRAM FOR 8: 1 MUX

Truth Table for 8 to 1 Multiplexer

TRUTH TABLE

VHDL CODE FOR 8:1 MUX :

Entity mux ;

    Port (S0: in STD_LOGIC;

    S1 :in STD_LOGIC;

    S2 :in STD_LOGIC;

 IN0 :in STD_LOGIC;

   IN1 :in STD_LOGIC;

   IN2 :in STD_LOGIC;

   IN3 :in STD_LOGIC;

   IN4 :in STD_LOGIC;

   IN5 :in STD_LOGIC;

   IN6 :in STD_LOGIC;

   IN7 :in STD_LOGIC;

   Y :out STD_LOGIC );

  End mux ;

Architecture behavioral of mux is

Signal a0,a1,a2,a3,a4,a5,a6,a7:BIT;

begin

a0 <= IN0 and (not s0) and (not s1) and (not s2);

a1 <= IN1 and (not s0) and (not s1) and        s2;

a2 <= IN2 and (not s0) and        s1   and (not s2);

a3 <= IN3 and (not s0) and        s1   and        s2;

a4 <= IN4 and    s0     and (not s1) and (not s2);

a5 <= IN5 and    s0     and (not s1) and        s2;

a6 <= IN6 and    s0     and         s1  and (not s2);

a7 <= IN7 and    s0     and         s1  and        s2;

     

Y <= a0 or a1 or a2 or a3 or a4 or a5 or a6 or a7

    end behavioral;

Demultiplexer

• A Demultiplexer is a combinational logic circuit that receives information on a single line and transmits this information on one of 2ⁿ possible output lines.
• Demultiplexer is also known as one input and many outputs.

1 to 8 Demultiplexer

In 1 to 8 demultiplexer, 1 represents demultiplexer input and 8 represents the number of output lines.

Logic Diagram for 1 to 8 Demultiplexer

CIRCUIT DIAGRAM FOR 1 : 8 DEMUX

Truth Table for 1 to 8 Demultiplexer

TRUTH TABLE

VHDL CODE FOR 1:8 DEMUX :

Entity Demux ;

Port (S0: in STD_LOGIC;

S1 :in STD_LOGIC;

S2 :in STD_LOGIC;

d0 :out STD_LOGIC;

d1 :out STD_LOGIC;

d2 :out STD_LOGIC;

d3 :out STD_LOGIC;

d4 :out STD_LOGIC;

d5 :out STD_LOGIC;

d6 :out STD_LOGIC;

d7 :out STD_LOGIC;

O :in STD_LOGIC );

end Demux ;

Architecture behavioral of Demux is

begin

Process(S2 , S1 , S0 , O )

begin

d0 <= (not s2) and (not s1) and (not s0) and O;

d1 <= (not s2) and (not s1) and     s0      and O;

d2 <= (not s2) and    s1       and (not s0) and O;

d3 <= (not s2) and    s1       and     s0      and O;

d4 <=        s2   and (not s1) and (not s0) and O;

d5 <=        s2   and (not s1) and     s0      and O;

d6 <=        s2   and    s1       and (not s0) and O;

d7 <=        s2   and    s1       and     s0      and O;

end Process;

end behavioral;